■Wide dot clock range suited for TV Signal (480i-1080p), PC Signal (VGA-QXGA)
TTL/CMOS Input: 10-160MHz
LVDS Output: 20-160MHz
■PLL requires No external components
■Flexible Input/Output mode
1.Single/Dual TTL IN, Single/Dual LVDS OUT
2.Double edge input for Single TTL IN/Dual LVDS OUT
3.Input port SW for Single TTL IN/Dual LVDS OUT
4.Asynchronous Dual TTL IN/Dual LVDS OUT
■Clock edge selectable
■3 LVDS data mapping for simplifying PCB layout.
■Pseudo Random pattern generation circuit
■Supports Reduced swing LVDS for Low EMI
■Power down mode
■Low power single 3.3V CMOS design
■Backward compatible with THC63LVD1023
■144pin LQFP